Computing at the fundamental physical limits

Foundation builds semiconductor IP for heterogeneous computing.

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Every compute architecture has different algorithmic advantages.

Five separate chips, each on its own package. A CPU, a GPU, a dataflow accelerator, an in-memory compute chip and a quantum processor, each with a different layout on its die.
CPUSerial, branch-heavy control codeGPUMassively parallel arithmeticDataflow acceleratorTensor pipelinesIn-memory computeMemory-bound kernelsQuantum processorSimulating quantum systems

Interfacing them requires new building blocks for chips.

The same five chips on one shared substrate, with an empty dashed slot between each pair. Callouts name what differs between neighbors, from instruction sets and clocks to data formats and temperature.
Different instruction setsDifferent clocks and signalingDifferent data formatsRoom temperature to millikelvin
Different instruction setsDifferent clocks and signalingDifferent data formatsRoom temperature to millikelvin

That’s what we tackle.

The same five chips joined by glowing interconnect blocks in each slot, with a translucent architecture layer floating above all of them and dashed lines dropping to every chip.
Architecture layerOne instruction set and compiler for every chipInterconnect blocksCoherent links, SerDes and front ends
Architecture layerOne instruction set and compiler for every chipInterconnect blocksCoherent links, SerDes and front ends

AI-aided chip design

We design across quantum, photonic, analog, mixed-signal and digital domains at once, with AI agents that turn one specification into layouts for every domain together.

One specification
A single description of the system drives the photonics, the electronics and the architecture, so the blocks are designed together rather than stitched together after the fact.
Agents per domain
Language-model agents work on each domain in parallel and trade the budgets the domains share, such as power, area and timing.
Checked before layout
Every proposal is checked against simulation and machine-checked proofs before it reaches layout.

How we work

We design the semiconductor IP and license it, working closely with the customer to bring it to production.

  1. Customize

    We fit a block to one of your products, its process and its package.

  2. Tape out together

    The block goes out on your run and you measure it on your own package. The silicon and the measurements are yours to keep.

  3. License

    You license the IP, and we work with your team until it is in production.

Company

Foundation Silicon, Inc. was founded on research from Caltech and MIT, and is based at the Caltech Innovation Center and the Engine at MIT.

Founder

Volkan Gurses on LinkedIn
Founder and CEO

Advisors